(China (Mainland))
Product Summary
The PPC405EP-3LB333C is a PowerPC 405EP Embedded Processor. Designed specifically to address embedded applications, the PPC405EP-3LB333C provides a high-performance, low-power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation requirements. This chip contains a high-performance RISC processor core, SDRAM controller, PCI bus interface, Ethernet interface, control for external ROM and peripherals, DMA with scatter-gather support, serial ports, IIC interface, and general purpose I/O.
Parametrics
PPC405EP-3LB333C absolute maximum ratings: (1)Supply Voltage (Internal Logic), VDD: 0 to +1.95 V; (2)Supply Voltage (I/O Interface), OVDD: 0 to +3.6 V; (3)PLL Supply Voltage, AVDD: 0 to +1.95 V; (4)Input Voltage (1.8V CMOS receivers), VIN: 0 to +1.95 V; (5)Input Voltage (3.3V LVTTL receivers), VIN: 0 to +3.6 V; (6)Input Voltage (5.0V LVTTL receivers), VIN: 0 to +5.5 V; (7)Storage Temperature Range, TSTG: -55 to +150℃; (8)Case temperature under bias, TC: -40 to +120℃.
Features
PPC405EP-3LB333C features: (1)AMCC PowerPC 405 32-bit RISC processor core operating up to 333MHz with 16KB Dand I-caches; (2)PC-133 synchronous DRAM (SDRAM) interface, 32-bit interface for non-ECC applications; (3)4KB on-chip memory (OCM); (4)External peripheral bus, Flash ROM/Boot ROM interface; Direct support for 8- or 16-bit SRAM and external peripherals; Up to five devices; (5)DMA support for memory and UARTs, Scatter-gather chaining supported; Four channels; (6)PCI Revision 2.2 compliant interface (32-bit, up to 66MHz), Asynchronous PCI Bus interface; Internal or external PCI Bus Arbiter; (7)Two Ethernet 10/100Mbps (full-duplex) ports with media independent interface (MII); (8)Programmable interrupt controller supports seven external and 19 internal edge-triggered or level-sensitive interrupts; (9)Programmable timers; (10)Software accessible event counters; (11)Two serial ports (16750 compatible UART); (12)One IIC interface; (13)General purpose I/O (GPIO) available; (14)Supports JTAG for board level testing; (15)Internal processor local bus (PLB) runs at SDRAM interface frequency; (16)Supports PowerPC processor boot from PCI memory.
Diagrams
